1. Field of the Invention
The present invention relates to a method of fabricating a capacitor, and more particularly to a method of forming a trench-type capacitor in a dynamic random access (DRAM).
2. Description of the Related Art
Integrated circuits (IC) are widely used in semiconductor industry. All kinds of semiconductor devices are produced according to different objects. These devices have high efficiency and lower cost. For example, DRAM devices are important in the electronic industry. A DRAM cell is composed of a transistor and a capacitor. In FIG. 1, the arrangement of a DRAM cell is shown. The drain of the NMOS transistor 10 is connected to a storage plate of a capacitor 20. The gate of the NMOS transistor 10 is connected to a word line WL. The source of the NMOS transistor 10 is connected to a bit line BL. Additionally, an opposed plate of the capacitor 20 is connected to a power source. Further, a dielectric layer is disposed between the storage plate and the opposed plate. The capacitor stores or releases charges according to the ON or OFF state of the NMOS transistor. Thus, the logic memory of a memory cell is performed.
A planar-type capacitor is used in the fabrication of a DRAM whose memory capacity is below 1MB. As the arrangement of the capacitor is two dimensional, the area of the plate distributed in the substrate is large so as to provide enough memory capacity. However, as sizes of devices are decreased, the size of the DRAM device is minimized also. In the planar-type capacitor, minimizing the distributing area of the plates will decrease the capacitance of the capacitor.
To solve the problems described above, a capacitor with three dimensions has been proposed. For example, a trench-type capacitor or a stacked-type capacitor is well known in the field. The trench-type capacitor and the related arts is disclosed in U.S patent application Ser. No. 5,395,786, No. 5,658,816, and a paper entitled "A 0.6 .mu.m 256 Mb Trench DRAM Cell With Self-aligned BuriEd Strap (BEST)" published in 1993 IEDM p. 627.about.P. 630 by L. Nesbit, et al. This type of capacitors has increased capacitance but takes a smaller area of the substrate. In the processes of forming a trench-type capacitor, an insulating layer (for example, oxide/nitride or oxide/nitride/oxide) and a conducting layer (for example, a polysilicon layer doped with N.sup.+ ions) are deposited and etched to form the structure of the trench-type capacitor. In the normal processes, a mask is formed utilizing photoresist on substrate. Utilizing photolithography, a trench is subsequently formed. Then a plate and a dielectric layer are successively formed in the trench. Thereupon, the trench is filled with a conducting material, and then a trench-type capacitor is formed.
FIG. 2A.about.FIG. 2F show the processes of forming a trench-type capacitor in a substrate as described in the paper entitled "A 0.6 .mu.m 256 Mb Trench DRAM Cell With Self-aligned BuriEd Strap (BEST)" published in 1993 IEDM p. 627.about.P. 630 by L. Nesbit, et al. As shown in FIG.2A, an epitaxy layer 210 is formed on the P.sup.- -type substrate 200. Subsequently, a silicon oxide layer 220 and a silicon nitride layer 221 are formed on the epitaxy layer 210. Then a first trench 230 is formed by utilizing photolithography and etching technologies, wherein the bottom of the trench 230 is in the P.sup.- -type substrate 200.
Referring to FIG. 2B, in order to form a storage plate 240, arsenic ions are driven into the bottom and the sidewalls of the trench 230 in the P.sup.- -type substrate 200 according to ion diffusion. The storage plate 240 is to be a plate of the trench-type capacitor formed thereafter. Then silicon oxide and silicon nitride (ON) are subsequently deposited in the bottom and the sidewalls of the trench 230 to form a dielectric layer 250. Thus, a second trench 231 is formed.
Referring to FIG. 2C, polysilicon doped with arsenic ions N.sup.+ is filled in the second trench 231. After a planarization process, a first conducting layer 260 is formed. Then the dielectric layer 250 exposed in the air is etched to form a dielectric layer 250' between the two plates of the trench-type capacitor formed thereafter. A third trench 232 is formed herein.
As shown in FIG. 2D, a collar isolation layer 270 and a second conducting layer 261 are formed in the trench 232. The material of the collar isolation layer 270 is silicon oxide in order to prevent leakage. The second conducting layer 261 is made of polysilicon doped with arsenic ions N.sup.+.
Referring to FIG. 2E, the collar isolation layer 270 and the second conducting layer 261 are selectively etched to form a collar isolation layer 270' and a second conducting layer 261'. It is noted that two materials are etched in the step, so it is necessary to set appropriate etching depths twice so that a fourth trench 233 is formed.
As shown in FIG. 2F, polysilicon doped with arsenic ions N.sup.+ is deposited in the fourth trench 233 to form a third conducting layer 262. A trench-type capacitor is then completed herein.
However, devices with high integration in a substrate are highly developed in the semiconductor industry. Take a DRAM for example. In order to obtain better-integrated memory, a large number of memory cells must be fit in a memory circuit; thus, the base area of a memory cell must be minimized. It is well known that the capacitance of a capacitor is in proportion to the area of the plate. Thus, the amounts of charges that the capacitor can store are decreased.